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Session: WE4D3:30 PM Wednesday, May 26, 2010 Room: 207C |
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Session: WE4D | High-speed Signal Processing Circuits for Wireless and Optical Communication Systems |
Chair: | Koichi Murata, NTT Photonics Labs. |
Co-Chair: | Edward Gebara, Georgia Institute of Technology |
Abstract: | This session presents state-of-the-art broadband ADC and DAC circuits in CMOS and BiCMOS technologies for high-speed communication systems. Additionally, 60-GHz mixed-signal and signal processing circuits in pure CMOS are being introduced that shows Giga-bit wireless transmissions. Furthermore, this session introduces an InP-based ultra-broadband amplifier for 100-Gbit/s fiber communication systems. |
| | WE4D-1 | A 50-GS/s 5-b ADC in 0.18-um SiGe BiCMOS | 3:30 PM-3:50 PM | J. Lee, Y. Chen, Alcatel-Lucent, Murray Hill, United States |
(1594) | A 5-b 50-GS/s ADC is presented in 0.18-um SiGe BiCMOS. The two-channel interleaved flash architecture is used to increase the conversion rate. The front-end three-stage distributed track-and-hold amplifier is devised to improve the dynamic performance. The ADC features SNDR as high as 23.1 dB with 20 GHz sine wave input at 50 GS/s conversion rate, and the third harmonic distortion is -36.5 dBc. It shows the measured resolution bandwidth of 18 GHz and the FOM of 9 pJ per conversion step with power consumption of 5.4 W. | | |
WE4D-2 | A 17pJ/bit Broadband Mixed-Signal Demodulator in 90nm CMOS | 3:50 PM-4:10 PM | K. S. Chuang, D. Yeh, F. Barale, B. Perumana, S. Sarkar, P. Sen, S. Pinel, J. Laskar, Georgia Electronic Design Center, Atlanta, United States |
(1236) | This paper presents the first fully integrated mixed-signal demodulator incorporating ultra low-power 3mW 3Gsps 3-bit ADCs and a 2mW high-speed real-time digital signal processing in 90nm CMOS that requires neither external synchronization controls nor processing to demodulate up to 3.5Gbps binary phase-shift keying (BPSK) modulated signal. The demodulator is integrated with IQ mixers, 13GHz QVCO, frequency synthesizers and baseband AGC, for an overall power consumption of 60mW from a 1V supply. The entire demodulator chip occupies 1.275x1.19mm2 and enables error free demodulation up to 2.5Gbps and BER of 1E-09 up to 3Gbps. To the best of authors’ knowledge, this demonstrates the maximum throughput at minimum power budget among all types of CMOS multi-gigabit demodulators. | | |
WE4D-3 | Pulse Shaping and Clock Data Recovery for Multi-Gigabit Standard Compliant 60 GHz Digital Radio | 4:10 PM-4:30 PM | F. Barale, G. B. Iyer, B. G. Perumana, P. Sen, S. Sarkar, A. Rachamadugu, N. Dudebout, S. Pinel, J. Laskar, Georgia Institute of Technology, Atlanta, United States |
(1145) | This paper presents the first ultra low power (5 mW) multi-gigabit pulse-shaping filter and clock data recovery circuits fully integrated in a 90-nm CMOS wireless digital radio meeting the specifications of 60 GHz wireless standards. The architecture features a 4.4 Gsps capable 13-tap FIR pulse shaping filter on the TX side, and a dual loop clock data recovery on the RX side to suppress the high frequency jitter introduced by the pulse shaping. Using a fully integrated 60 GHz TDD transceiver embedding the presented solution, a 95% reduction of the high frequency jitter has been measured at the standard nominal 1.728 Gbps data rate. The solution features a minimal power overhead of 5 mW from 1 V voltage supply. | | |
WE4D-4 | A 1 V 6-bit 2.4 GS/s Nyquist CMOS DAC for UWB Systems | 4:30 PM-4:50 PM | B. Kim, M. Cho, Y. Kim, J. Kwon, Electronics and Telecommunications Research Institute, Daejeon, Republic of Korea |
(1048) | A 6-bit 2.4 GS/s current-steering DAC fabricated in a 65 nm CMOS technology for ultra-wideband (UWB) systems is presented. The prototype achieves a measured spurious-free dynamic range (SFDR) of more than 36 dB over the Nyquist bandwidth at 2.4 GS/s. Among the 50 measured samples, DNL/ INL of 0.02/0.02 LSB was the lowest achievable value. The DAC core occupies an area of merely 0.023 mm2 through simplified circuit and careful layout. To operate from a relatively low analog power supply of 1 V, a portion of current cell is implemented using low threshold voltage devices. Total maximum power consumption, including the low voltage differential signaling (LVDS) stage, is 14 mW at 2.4 GS/s. | | |
WE4D-5 | A 6 Bit Linear Binary RF DAC in 0.25µm SiGe BiCMOS for Communication Systems | 4:50 PM-5:00 PM | M. Khafaji, H. Gustat, J. Scheytt, IHP Microelectronics, Frankfurt Oder, Germany |
(1529) | This paper presents a circuit technique to improve the frequency domain behavior of the binary weighted digital to analog convertors (DAC). It is shown that by adding a current buffer stage, the effect of one of the major drawbacks in this architecture, the impedance variation in every stage, is reduced. To verify the method, a fully binary 6bit 20.5Gsps DAC with 1W power dissipation and measured SFDR higher than 28.2dBc up to 6.2GHz input bandwidth was fabricated. The DAC produces 1Vpp differential output, and less than 60ps full scale rise time. | | |
WE4D-6 | Distributed Amplifiers in InP DHBT for 100-Gbit/s Operation | 5:00 PM-5:10 PM | J. Y. Dupuy, A. Konczykowska, F. Jorge, M. Riet, J. Godin, Alcatel-Lucent, Marcoussis, France |
(1439) | Two single-ended distributed amplifiers were designed and fabricated using a 0.7-μm InP double heterojunction bipolar transistor (DHBT) technology. The first amplifier’s gain and bandwidth are respectively around 15 dB and 90 GHz. The second amplifier’s gain and bandwidth are respectively higher than 13 dB and 110 GHz. Eye diagram measurements were performed at 86 Gbit/s showing clear eye opening and large output swing, respectively as high as 2.7 Vpp and 2.4 Vpp, for the first and second amplifier. These distributed amplifiers are well suited for a use as modulator drivers for 100 Gbit/s optical communication systems. | | |
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