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Session: Poster8:00 AM Friday, June 20, 2008 Room: Omni Hotel |
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Session: Poster | Interactive Forum |
Chair: | Chris Ward, Jacket Micro Devices |
| | Poster-1 | An Advanced Full Path Loop-back Testing Techniques for Embedded RF Identification (RFID)System-on-a-Chip (SoC) Applications | - | B. Kim, I. Park, D. Yoo, J. Koo, I. Kim, B. Choi, Y. Bae, B. Kim, Samsung Electronics, Yongin-City, Republic of Korea |
(24) | The full path loop-back test without use of the RF option in the ATE that can accommodate embedded RFID SoCs has been proposed. The advanced testing techniques have been carried out using test vectors to generate the modulated sinusoidal waves. In addition, no RF option in the ATE is used for evaluating RF block in SoC module. The proposed techniques are encouraging developments for reducing the test of cost in the ATE without the use of RF option and for validating SoC full path test. | | |
Poster-2 | High power on-wafer capabilities of a time domain load-pull setup | - | F. De Groote1, J. Teyssier2, J. Verspecht3, J. Faraj2, 1Verspecht-Teyssier-DeGroote SAS, Brive, France, 2XLIM Limoges University, Brive, France, 3Jan Verspecht bvba, Opwijk, Belgium |
(12) | High power LSNA on-wafer measurements up to 20 Watts at 2 GHz have been performed on a 3.2 mm gate width AlGaN/GaN HEMT. Time domain slopes in pulsed mode are given for different pulsed drain voltages, showing the importance to monitor the drain voltage and current slopes, as they are directly linked to the transistor reliability. At such power range, the LSNA on-wafer load-pull setup with two ‘wave probes’ couplers demonstrates its capabilities to handle up-todate power transistors in the S band, and to provide the time domain information usually missing with classical load-pull setups. | | |
Poster-3 | A Load-Pull Wafer-Mapper | - | F. Vanaverbeke, K. Vaesen, L. Pauwels, W. De Raedt, M. Germain, S. Degroote, J. Das, J. Derluyn, X. Dongping, S. Dominique, Imec vzw., Heverlee, Belgium |
(19) | This paper describes an automated load-pull measurement testbench for the characterization of GaN power HEMTs. The setup was built around a vector network analyzer (VNA) and an electromechanical tuner. The setup is combined with a semi-automatic wafer-stepper, allowing for complete large-signal wafer-mapping. Both calibration and measurement procedure are explained in mathematical detail. | | |
Poster-4 | On-Chip Cancellation of Parasitic Effects for Dielectric Permittivity Measurement | - | C. Song, P. Wang, Clemson University, Clemson, United States |
(11) | A new approach for parasitic effects cancellation is proposed, analyzed, and experimentally evaluated. The method exploits the symmetry of the proposed test structures. It greatly improves measurement sensitivity for small dielectric permittivity changes. The experimental results agree well with theoretical and simulation results. | | |
Poster-5 | Measurement Uncertainty of Direct Power Measurement using the Pulse Sensor MA2411B | - | Y. Lee, Anritsu, Morgan Hill, United States |
(29) | Typical power measurement references to the point value of 1 mW at 50 MHz. This point provides a traceability path to the National Standard for microwave power measurement. The Anritsu MA2411B pulse sensor starts with a low end of 300 MHz. Therefore, the reference power is set at 1 GHz. This report discusses the details of the test procedures and uncertainty budget in establishing specifications of reference output power uncertainty for the combination of power meter ML2488A and power sensor MA2411B. We will review different sensor and meter options when making a direct power measurement. A detailed uncertainty budget will be presented when making direct power measurement using the MA2411B. All uncertainty budgets are based on the guideline of the ISO Guide to the Expression of Uncertainty in Measurement (GUM) [1]. | | |
Poster-6 | Verification of wafer-level calibration accuracy at high temperatures | - | A. Rumiantsev1, R. Doerner2, 1SUSS MicroTec Test Systems GmbH, Sacka OT Thiendorf, Germany, 2Ferdinand-Braun-Institut fuer Hoechstfrequenztechnik (FBH), Berlin, Germany |
(32) | This article presents the results of accuracy verification of wafer-level calibration at high temperatures based on coplanar calibration standards. The electrical characteristics of different commercially available coplanar calibration lines were extracted and compared at different temperatures. Finally, the accuracy of lumped calibrations at variable temperatures was verified by definition of the worst-case error bounds for the measurement of passive devices and compared to the reference NIST multiline TRL. | | |
Poster-7 | Quantitative Understanding of the Mated Interface Characteristics of Precision Coaxial Connectors at Microwave and Millimeter-Wave Frequencies | - | M. Horibe, M. Shida, K. Komiyama, National Metrology Institute of Japan, Tsukuba, Japan |
(23) | This paper is investigation of inter-mate ability of precision coaxial connectors for the mated interface made of connectors produced by different manufacturers. The connectors were usually designed on the basis of IEEE or IEC standards, however, dimensions of the female socket and male pin vary by manufacturer. As a result, the different reflection characteristics generated around the mated interfaces depend on the combination of connectors supplied by different manufacturers. This investigation is based on dimensional assessment and further time-domain reflection measurement. The paper includes an analysis and discussion of the influence of connector mated interface to the measurements using Vector Network Analyzers. | | |
Poster-8 | A Method for Automatic Tuner Verification | - | E. M. Johnson, Freescale Semiconductor, Tempe, United States |
(21) | This paper describes an automated procedure for verifying the characterization of mechanical tuners used in automated load-pull systems. Precise tuner characterization is critical for making accurate load-pull measurements, as small inaccuracies in the tuner S-parameters can lead to significant errors in measured results. A software routine was written to automate the tuner verification process by controlling a vector network analyzer and a tuner controller. The program is easy to use, customizable, quick, and low-cost to implement. Results are automatically summarized, describing the tuner’s S-parameter accuracy in terms of error vector magnitude (EVM). Example results are shown for tuners with accurate and inaccurate characterizations. | | |
Poster-9 | Characterization of Carbon Nanotube Field Effect Transistors using an active load pull LSNA setup | - | C. Gaquiere1, A. Curutchet3, D. Theron1, M. Werquin2, D. Ducatteau1, J. M. Bethoux1, H. Happy1, G. Dambrine1, V. Derycke4, 1IEMN, Villeneuve d'Ascq, France, 2MC2 technologies, Villeneuve d'Ascq, France, 3IMS, Talence, France, 4CEA, Gif sur yvette, France |
(14) | CNFETs have been characterized under large signal conditions at 600 MHz with an original active load pull setup using a LSNA. A non linear model of CNFET has been established and validated by comparison with the experimental results. Using this non linear model, design of circuits can be considered, allowing the optimization in non linear behavior. | | |
Poster-10 | A Proposed VNA Calibration Requirement for Traceability | - | X. Liu1, H. Huang1, Y. Lee2, 1National Institute of Metrology, Beijing, China, 2Anritsu Company, Morgan Hill, United States |
(28) | The status of calibration service for vector network analyzers (VNAs) is introduced. Some recommendations are proposed to provide an efficient and traceable calibration service for VNA. | | |
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