IEEE MTT-S 2008 International Microwave Symposium Technical Program

Session: WE1B	Novel Low Phase Noise Techniques for VCO's and Synthesizers.
Chair:	Danny Elad, IBM
Co-Chair:	Yi-Jan Emery Chen, National Taiwan University
Abstract:	This session presents papers on novel design techniques to achieve low phase noise in VCOs and Synthesizers. Papers in this sesion include frequency synthesizer for UWB applications, VCOs utilizing metamaterial transmission lines, SiGe HBT VCOs, BJT STCPR VCOs and CMOS QVCO.

WE1B-01	A 1.5-V 3~10-GHz 0.18-um CMOS Frequency Synthesizer for MB-OFDM UWB Applications
1091	Z. Huang, F. Kuo, W. Wang, C. Wu, Nanoelectronics and Gigascale Systems Laboratory, Hsinchu, Taiwan
	An Ultra wide band (UWB) frequency synthesizer is designed and fabricated in 0.18-μm CMOS technology to generate all the carrier frequencies for 13 bands distributed from 3 to 10 GHz. It is composed of one phase-locked loop (PLL) and three single-side band (SSB) mixers. The polyphase filter is used to generate all needed quadrature signals in the circuit and band selectors are to select the frequency band. The sideband rejection can be over 30dB. The switching time between bands is around 3.75ns. The current consumption is 72mA under 1.5-V power supply.

WE1B-02	STPCR Offers Integrable Alternatives Of DRO
1057	U. L. Rohde², A. K. Poddar¹, ¹Synergy Microwave Corp., Paterson, United States, ²University of Cottbus, Cottbus, Germany
	This paper describes the STPCR (Stubs-Tuned Planar Coupled Resonators) based VCO that offers cost-effective and integrable alternative for DRO (Dielectric Resonator Oscillators) circuits. The measured phase noise is typically –122 dBc/Hz at 100 kHz offset from a 12 GHz carrier with 400 MHz tuning, and 13.8 % DC-to-RF conversion efficiency. Index Terms — DC-to-RF, DRO, STPCR, VCO.

WE1B-03	A Low-Voltage Low-Phase-Noise Bottom-Series LC QVCO Using Capacitor Tapping Technique
1722	Y. Zhang¹, P. Liu¹, J. Jung¹, T. Luo², Y. E. Chen², D. Heo¹, ¹Washington State University, Pullman, United States, ²National Taiwan University, Taipei, Taiwan
	This paper presents a novel low-voltage low-phase-noise LC quadrature voltage controlled oscillator (QVCO) implemented in TSMC 0.18-µm CMOS process. By using a combination of bottom-series coupling architecture and capacitor tapping technique, the QVCO achieves a zero resonator phase shift (RPS), a high loaded resonator quality factor, and limited phase noise contribution from the current source, all of which lead to a low phase noise. From a 5.3-GHz carrier, the measured phase noise is -123 dBc/Hz at 1-MHz offset with a 1.8-V power supply and -118 dBc/Hz at 1-MHz offset with a 1-V power supply.

WE1B-04	Dual-Band VCO using Composite Right/Left-Handed Transmission Line and Tunable Negative Resistance based on Pin Diode
1480	J. Choi, C. Seo, Soongsil University, Seoul, Republic of Korea
	In this paper, the dual-band voltage-controlled oscillator (VCO) using the composite right/left-handed (CRLH) transmission line (TL) and the tunable negative resistance based on the pin diode is presented. It is demonstrated that the CRLH TL can lead to metamaterial transmission line with the dual-band tuning. The dual-band of the CRLH TL is achieved by the frequency offset and the phase slope of the CRLH TL. The tunable negative resistance based on the pin diode has been used to operate the dual-band of VCO. The phase noise of VCO is -108.34 ~ -106.67 dBc/Hz @ 100 kHz in the tuning range, 2.423 ~ 2.597 GHz for the forward bias of the pin diode, whereas that of VCO is -114.16 ~ -113.33 dBc/Hz @ 100 kHz in the tuning range, 5.137 ~ 5.354 GHz for the reverse bias of the pin diode.

WE1B-05	A High Sensitivity, Low Power Phase Controlled Current Source for GSamples/s Phase-Locked Loops
1138	T. Chien, C. Lin, D. Chang, Y. Juang, C. Huang, National Chip Implementation Center, National Applied Research Laboratories, Hsinchu City, Taiwan
	Operating up to 3.2-GHz with power consumption of 1.32mW, a Phase Controlled Current Source (PCCS) capable of both phase frequency comparing and current providing is presented. Benefiting from simple, feed-forward operation characteristic, the PCCS minimizes the short current issue while maintaining free dead zone feature. The phase and frequency sensitivities of the PCCS have been measured to demonstrate its performance. With a reference source ranging from 2.1-GHz to 3.2-GHz, a PLL embedding the PCCS achieves phase noise around -100 dBc/Hz at 1-kHz offset. The lowest phase noise at 1MHz offset is -131 dBc/Hz when the PLL uses a 2.3-GHz reference source.

WE1B-06	Low-Phase-Noise SiGe HBT VCOs Using Trifilar-Transformer Feedback
1299	C. Meng¹, J. Syu¹, S. Tseng¹, Y. Chang¹, G. Huang², ¹National Chiao Tung University , Hsinchu, Taiwan, ²National Nano Device Laboratories, Hsinchu, Taiwan
	The SiGe heterojunction bipolar transistor (HBT) voltage controlled oscillators (VCOs) using trifilar-transformer feedback at emitters, bases and collectors are demonstrated. The integrated trifilar transformer can allow dual voltage swings across the collectors and emitters of a cross-coupled differential pair and separate the bias between bases and collectors to optimize the output power. The tank inductance is also improved by the mutual coupling of the trifilar transformer. Thus, 191 dBc/Hz FOM (figure of merit) is achieved and is comparable to that of the state-of-the-art VCO.

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