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Session: TH2B10:10 AM Thursday, June 19, 2008 Room: A312 |
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Session: TH2B | Advanced high efficiency power amplifier concepts |
Chair: | Anh-Vu Pham, UC Davis |
Co-Chair: | Leo de Vreede, TUDelft |
Abstract: | In this session various efficiency enhancement techniques will be covered, ranging from switch mode, to adaptive load modulation. We start with 90% GaAs-HBT and GaN HEMT amplifiers for software defined radio and followed by an all-digital CMOS approach to serve ZigBee applications. New approaches are tested for their functionality using extensions to traditional LINC and Doherty Amplifier concepts. The session is completed with a discussion of a novel sequential power amplifier. |
| | TH2B-01 | Switch-Mode Amplifier ICs with over 90% Efficiency for Class-S PAs using GaAs-HBTs and GaN-HEMTs | 1356 | C. Meliani, J. Flucke, A. Wentzel, H. Wuerfl, W. Heinrich, G. Traenkle, Ferdinand-Braun-Institut fuer Hoechstfrequenztechnik, Berlin, Germany |
| This paper reports on design and realization of monolithic switch-mode amplifiers for data rates up to 1.8 Gbps, suitable for Class-S and inverse class-D PA modules. GaN HEMT as well as high-voltage GaAs-HBT technologies are employed and compared. For digital signal transmission without output filter-ing, the chips achieve efficiencies of more than 90 % at an output power of 5.4 W and 6.5 W with PAE values including the on-chip drivers, of 75% and 80% for GaAs-HBT and GaN-HEMT Ics respectively. These high efficiencies values are very promising since such PA chips represent the key building block for future class S systems. | | |
TH2B-02 | An All-Digital CMOS 915 MHz ISM Band 802.15.4 / ZigBee Transmitter with a Noise Spreading Direct Quantization Algorithm | 1625 | J. Rode, T. Hung, P. Asbeck, University of California, San Diego, La Jolla, United States |
| This paper presents an all-digital CMOS class-D transmitter system for the 915 MHz ISM band using 802.15.2/ZigBee standards. A novel noise spreading quantization algorithm which derives the digitally modulated amplifier input is presented. This new algorithm requires fewer DSP cycles than delta-sigma approaches, while still maintaining high amplifier efficiency and meeting spectral specifications. The entire transmitter is easy to integrate into modern submicron CMOS processes. The power amplifier achieves a peak drain efficiency of 57%, while the overall transmitter system achieves a DC/Data-to-RF efficiency of 22%. The CMOS power amplifier is capable of a maximum power output of 18 mW while meeting 802.15.2 specifications. | | |
TH2B-03 | A Highly Efficient Chireix Amplifier Using Adaptive Power Combining | 1402 | J. Qureshi1, R. Lui1, M. V. Heijden2, J. Gajadharsing3, L. C. de Vreede1, A. J. de Graauw2, 1TuDelft, Delft, Netherlands, 2NXP, Eindhoven, Netherlands, 3NXP, Nijmegen, Netherlands |
| A novel, highly efficient out-phasing amplifier with adaptive power combiner is presented. Saturated class-F operation is used for the amplifier cells. Varactor tuning is applied to make the output power combining network adaptive. Use of optimum input drive conditions and output varactor tuning, to eliminate imaginary loading introduced by the out-phasing principle, yields an amplifier efficiency of more than 50% over a 9 dB power back-off range. | | |
TH2B-04 | A Novel Doherty Amplifier for Enhanced Load Modulation and Higher Bandwidth | 1675 | M. Sarkeshi1, O. B. Leong1, A. H. Roermund2, 1National University of Singapore, Singapore, Singapore, 2Technical University of Eindhoven, Eindhoven, Netherlands |
| We are reporting a new topology for the Doherty amplifier to increase its bandwidth and enhance the load modulation. A varactor-based impedance transformer has been employed to replace the bulky and narrowband quarter-wave impedance inverter. Load modulation is carried out adaptively using the proposed varactor-based structure based on the input power level. An envelope detector is employed for adaptive impedance transformation of the carrier amplifier as well as bias adaptation of the peak amplifier. Based on the proposed topology, a 2W Doherty amplifier has been fabricated using discrete pHEMT transistors and low loss varactors. Power added efficiency of better than 45.3% has been achieved. Measured IM3 is better than -42.2dBc at P1dB of 33dBm. | | |
TH2B-05 | Design And Performance Of Sequential Power Amplifiers | 1224 | T. Lehmann, R. Knoechel, Microwave Research Laboratory, Kiel, Germany |
| The paper presents an analysis of a sequential power amplifier (SPA) in a transmitter with an FPGA-circuit at the input and a directional coupler at the output. The nonlinear combining characteristics of the output coupler are investigated. The coupling strength and the ratio of maximum power of peaking and main amplifier are discussed as design parameters. A switched coupler is examined as the combiner. Due to the sequen-tial transmitter concept the back-off efficiency can be significantly increased. E.g. using conventional class-B amplifiers a 10 dB back-off efficiency of 38% can be achieved. The average power added efficiency of the whole transmitter may be im-proved by 30% compared to conventional amplifiers. Design trade offs, theoretical performance and measurement results of the proposed transmitters are presented. | | |
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